1. Field of the Invention
This invention generally relates to a semiconductor memory circuit, and, in particular, to a sense circuit for sensing the memory state of a memory cell in a semiconductor memory device, such as a read only memory (ROM), a programmable read only memory (PROM) or an erasable programmable read only memory (EPROM).
2. Description of the Prior Art
A typical prior art sense circuit for use in a semiconductor memory device is schematically shown in FIG. 6. A semiconductor memory device includes a plurality of memory cells, including a memory cell transistor M1, which are connected to a common sense point D1. The memory cell transistor M1 is connected between the sense point D1 and ground and has its gate connected to a word line W1 through a buffer circuit. Connected to each sense point D1 through an N-channel MOS transistor Q2a is a load P-channel MOS transistor for supplying current to a memory cell during read mode. The gate of the load MOS transistor Q1a is set at ground level during operation. A circuit C1 comprised of a P-channel MOS transistor Q3 and an N-channel MOS transistor Q4 is provided for detecting the level of voltage at the sense point D1, and the gate of the transistor Q4 is connected to the sense point D1. An interconnection node N1 between the MOS transistors Q3 and Q4 is connected to the gate of the MOS transistor Q2a. With this structure, the on/off state of the memory cell M1 is detected by the bit line voltage detecting circuit C1 as the voltage change at the sense point D1, and the impedance of the transistor Q2a is controlled, whereby the voltage level at the node N2a between the transistors Q1a and Q2a is varied. A circuit comprised of a P-channel MOS transistor Q5 and an N-channel MOS transistor Q6 serves to supply current to the sense point D1, together with the load MOS transistor Q1a, when the memory cell M1 is on, thereby controlling the lowering of the voltage at the sense point D1 so as to reduce the access time period.
FIG. 7 schematically shows another prior art sense circuit which is often found in a semiconductor memory device, typically ROM. In the structure shown in FIG. 6, the current supplying circuit comprised of the transistors Q5 and Q6 is controlled by the bit line voltage detecting circuit C1; whereas, in the sense circuit shown in FIG. 7, the current supplying circuit comprised of transistors Q5a and Q6a is controlled by a separately provided bit line voltage detecting circuit C1a. Other than that, the structures shown in FIGS. 6 and 7 are similar.
In such a sense circuit, a driver current Il of the load transistor is typically set between an on current Ioff Ion when the memory cell M1 is on and an off current when the memory cell M1 is off, so that Il is larger than Ioff but smaller than Ion. In this case, a sense margin for detecting the on state of the memory cell M1 is given by (Ion-Il) and a sense margin for detecting the off state of the memory cell M1 is given by (Il-Ioff). However, in such a sense circuit, changes of I1 and Ion do not compensate each other. As a result, there are brought about the following disadvantages. (1) Even if Ion fluctuates due to fluctuations in channel length and/or threshold voltage of a memory cell transistor, which are typically caused by fluctuations in manufacture, since I1, which is determined by the size of the load transistor Q1a, remains at constant, the sense margin at the on side, i.e., (Ion-Il), fluctuates. That is, for example, if I1 is set as shown in FIG. 8, when the on current Ion decreases, the on-side sense margin decreases, and, thus, the on-side access time period for detection of the on state increases as shown in FIG. 9. (2) The changes of Il are smaller as compared with changes of Ion due to fluctuations of supply voltage V.sub.cc, so that the on-side sense margin in this case also fluctuates. (3) In the case when Il changes due to fluctuations in transconductance, threshold voltage and/or channel length of the load transistor Q1a, which are caused by fluctuations in manufacture, and Ion remains at constant in contrast to case (1), the on-side sense margin also fluctuates.